module nco_naive (
           input wire clk,
           input wire rst_n,
           input wire [31: 0] fcw,
           input wire load,
           output wire [14: 0] lut_addr,
           input wire [11: 0] lut_data,
           output wire [11: 0] out,
           output wire out_valid
       );

reg [31: 0] phase_reg;
reg [31: 0] freq_reg;
reg [11: 0] out_reg;

wire [31: 0] addr;

assign addr = phase_reg + freq_reg;
assign lut_addr = addr[31: 17];
assign out = (freq_reg != 0) ? out_reg : 0;
assign out_valid = (freq_reg != 0) ? 1 : 0;

always @(posedge clk) begin
    if (!rst_n) begin
        phase_reg <= 0;
        freq_reg <= 0;
        out_reg <= 0;
    end else begin
        out_reg <= lut_data;
        phase_reg <= phase_reg + freq_reg;
        if (load) begin
            freq_reg <= fcw;
        end else ;
    end
end
endmodule
